[hatari-devel] Long mail : new cpu cores + 2 questions.

[Miro Kropáček]

> Is it still true if the data is misaligned on a byte ?
>
Of course not.


> Don't the cpu reads the lower part of the 1st word, then the 2nd word,
> then the upper part of the 3rd word ?
>
Yes, it does. What I'm actually not totally sure about is the number of bus
accesses in that case because 030 data cache works with longs, so in case
you place a word on a misaligned (odd) address and execute move.w (a0),d0,
according to 68030 UM it can generate up to 4 (!) bus accesses:

3:
2: <hi-byte>
1: <lo-byte>
0:

lea 1,a0
move.w (a0),d0 ; this ought to generate two bus cycles: 0-1 and 2-3 (the
word lies within the first long word)

but

5:
4: <hi-byte>
3: <lo-byte>
2:

lea 3,a0
move.w (a0),d0 ; this ought to generate 4 bus cycles: 0-1 and 2-3 (first
long word) and 4-5 and 6-7 (second long word)

As I'm not hardware guy I don't know if this is still true, i.e. if the
data cache really fetches long words even on 16-bit bus but it probably
makes sense (the CPU doesn't know anything about 16-bit bus) but on the
other hand, the burst mode is not possible because because of this HW
limitation according to Rodolphe Czuba so I really don't know.

Btw I'm sure you know it, just for the record -- move.b (a0),d0 takes the
same amount of time as (aligned) move.w (a0),d0

-- 
MiKRO / Mystic Bytes
http://mikro.atari.org
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.berlios.de/pipermail/hatari-devel/attachments/20111031/a741a922/attachment.html>